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| 型号： | NOIH2SM1000S-HHC |
| 厂商： | ON Semiconductor |
| 文件页数： | 51/67页 |
| 文件大小： | 0K |
| 描述： | IC SPACE IMAGE SENSOR 84-JLCC |
| 标准包装： | 1 |
| 系列： | HAS2 |
| 象素大小： | 18µm x 18µm |
| 有源象素阵列： | 1024H x 1024V |
| 电源电压： | 3.3V |
| 类型： | CMOS 成像 |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
| 其它名称： | CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCS-ND |
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NOIH2SM1000A
The column amplifier output is a stream of raw or
FPN-corrected pixels. These pixels then pass the
programmable gain amplifier, where gain and DC-offset can
be adjusted. Then follows a signal multiplexer that selects
between the pixel signal or the temperature sensor and four
externally-accessible analog inputs. The output of the
multiplexer is buffered and then made available at output
pad SIGNAL_OUT.
The PGA must be calibrated periodically with a black
reference input signal, triggered by CAL. After each change
of the gain settings, the PGA have to be calibrated to set the
correct offset on the PGA. It is suggested to make this CAL
signal equal to the BLANK signal.
NOTE: The BLANK signal resets the X shift register.
So after each active BLANK period, there has to
be a SYNCING of the x shift register before
reading out any pixel.
For gain and offset control, see section “Sensor
Programming” on page 52.
t 1
t 2
Description
CAL width
CAL-to-pixel-readout
Min
200 ns
50 ns
Typ
Max
Remarks
Multiplexer Operation
MODE.PGA[2..0]
000
001
010
011
100
101
110
111
Selected Input
pixel array
TEMP
-
-
AIN1
AIN2
AIN3
AIN4
? When pixel 56 comes out, stop the x clock after the
falling edge.
? The output stays at the same level of this pixel (see
Figure 38 on page 50)
? Change the gain settings by setting the internal registers
as described in Sensor Programming on page 52
? Assert the CAL signal for 200 ns but leave the BLANK
signal inactive
? After the CAL signal has felled down, wait 50 ns.
? Reactivate the X clock starting with the rising edge
? The first pixel that comes out is pixel 57
Changing gain during read out
It is possible to change the gain settings during the read out
of one line. The following procedure is suggested. For
example, gain changing between pixel 56 and 57.
Hard Reset ? Soft Reset ? Hard ? to ? Soft Reset
See Reset Modes Timing Controls on page 57.
The total time needed to change the gain settings is about
450 ns.
analogue? in?
CLK_AD C ?
t 1
t 3
t 2
DATA[11..0]?
XXX?
1
2
3?
t 4
Figure 41. ADC Timing Diagram
t 5
The ADC is a pipelined device that samples on each rising
edge of its clock CLK_ADC. The output DATA is updated
on each falling edge of CLK_ADC. There is an
input-to-output latency of 6.5 clock cycles.
t 1
t 2
Description
input setup
input hold
Min
5 ns
20 ns
Typ
Max
Remarks
t 3
t 4
t 5
sample clock
Latency
output delay
100 ns
6.5 t 3
10 ns
50% duty cycle required, ± 5%
exact
http://onsemi.com
51
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