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| 型号： | OR3T307S240-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 196 CLBS, 48000 GATES, PQFP240 |
| 封装： | PLASTIC, SQFP-240 |
| 文件页数： | 166/203页 |
| 文件大小： | 1368K |
| 代理商： | OR3T307S240-DB |
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Lattice Semiconductor
65
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI) (continued)
MPI Interface to FPGA
The MPI interfaces to the user-programmable FPGA
logic using a 4-bit address, read/write control signal,
interrupt request signal, and user start and user end
handshake signals. Timing numbers are provided so
that the user-logic data transfers can be performed syn-
chronously with the host processor (
PowerPC or i960)
interface clock or asynchronously. Table 18 shows the
internal interface signals between the MPI and the
FPGA user-programmable logic. All of the signals are
connected to the MPI in the upper-left corner of the
device except for the D[7:0] and CLK signals that come
directly from the I/O pin.
The 4-bit addressing from the MPI to the PLCs allows
for up to 16 locations to be addressed by the host pro-
cessor. The user address space of the MPI does not
address any hard register. Rather, the user is free to
construct registers from FFs, latches, or RAM that can
be selected by the addressing. Alternately, the decoded
address signals may be used as control signals for
other functions such as state machines or timers.
The transaction sequence between the MPI and the
user-logic is as follows. When the host processor ini-
tiates a transaction as discussed in the preceding sec-
tions, the MPI outputs the 4-bit user address (UA[3:0])
and the read/write control signal (URDWR, which is
read-high, write-low regardless of host processor), and
then asserts the user start signal, USTART. During a
write from the host processor, the user logic can accept
data written by the host processor from the D[7:0] pins
once the USTART signal is asserted. The user logic
ends a transaction by asserting an active-high user
end (UEND) signal to the MPI.
The MPI will insert wait-states in the host processor
bus cycles, holding the host processor until the user-
logic completes its task and returns a UEND signal,
upon which the MPI generates an acknowledge signal.
If the host processor is reading from the FPGA, the
user logic must have the read data available on the
D[7:0] pins of the FPGA when the UEND signal is
asserted. If the user logic is fast or if the MPI user
address is being decoded for use as a control signal,
the MPI transaction time can be minimized by routing
the USTART signal directly to the UEND input of the
MPI
. The timing section of this data sheet contains a
parameter table with delay, setup, and hold timing
requirements to operate the user-logic either synchro-
nously or asynchronously with the MPI host interface
clock.
The user-logic may also assert an active-low interrupt
request (UIRQ) to the MPI, which, in turn, asserts an
interrupt to the host processor. Assertion of an inter-
rupt request is asynchronous to the host processor
clock and any read or write transaction occurring in the
MPI
. The user-logic is responsible for providing any
required interrupt vectors for the host processor, and
the user-logic must deassert the interrupt request once
serviced. If the interrupt request is not deasserted in
the user logic, it will continue to be asserted to the host
processor via the MPI_IRQ pin.
Table 18. MPI Internal Interface Signals
Signal
MPI
I/O
Function
UA[3:0]
O
User Logic Address
. Addresses up to 16 unique user registers or use as control
signals.
URDWRN
O
User Logic Read/Write Control Signal
. High indicates a read from user logic by
the host processor, low indicates a write to user-logic by the host processor.
USTART
O
Active-High User Start Signal
. Indicates the start of an MPI transaction between
the host processor and the user logic.
UEND
I
Active-High User End Signal
. Indicates that the user-logic is nished with the
current MPI transaction.
UIRQ
I
Active-Low Interrupt.
Sends request from the user-logic to the host processor.
D[7:0]
FPGA I/O
User Data.
Eight data bits come directly from the FPGA pins—not through the
MPI
.
MPI_CLK
FPGA I
MPI
Clock.
The MPI clock is sourced by the host processor and comes directly
from the FPGA pin—not through the MPI.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相关PDF资料 |
PDF描述 |
|---|---|
| OR3T556PS240-DB | FPGA, 324 CLBS, 80000 GATES, PQFP240 |
| OR3T806PS240-DB | FPGA, 484 CLBS, 116000 GATES, PQFP240 |
| OR3T807PS240-DB | FPGA, 484 CLBS, 116000 GATES, PQFP240 |
| OR3T55-4BA256I | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
| OR3T55-4BA256 | FPGA, 324 CLBS, 40000 GATES, 80 MHz, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR3T30-7S240I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55 | 制造商:AGERE 制造商全称:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T55-4BA256I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS208I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T55-4PS240I | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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