152
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Compatibility with OR2C/TxxA Series
The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices
offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR2TxxA Series only), and all con-
guration pins.
The following restrictions apply:
1. There are two conguration modes supported in the OR2C/TxxA Series that are not supported in Series 3: mas-
ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor inter-
face (MPI) conguration modes that are unavailable in the OR2C/TxxA Series.
2. There are four pins—one per each device side—that are user I/O in the OR2C/TxxA Series which can only be
used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to
the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect
to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see item 3
below). See
Table 69 for a list of these pins in each package.
3. There are two other pins that are user I/O in both the OR2C/TxxA and Series 3 but also have optional added
functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connec-
tivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package. Table 69. Series 3 ExpressCLK Pins
Pin Name/
Package
144-Pin
TQFP
208-Pin
SQFP/SQFP2
240-Pin
SQFP/SQFP2
256-Pin
PBGA
352-Pin
PBGA
432-Pin
EBGA
I-ECKL
15
22
26
K3
N2
R29
I-ECKB
55
80
91
W11
AE14
AH16
I-ECKR
92
131
152
K18
N23
T2
I-ECKT
124
178
207
B11
B14
C15
I/O-SECKLL
33
49
56
W1
AB4
AG29
I/O-SECKUR
111
159
184
A19
A25
D5
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.