参数资料
型号: PEF22508E
厂商: INFINEON TECHNOLOGIES AG
元件分类: 数字传输电路
英文描述: DATACOM, PCM TRANSCEIVER, PBGA256
封装: 17 X 17 MM, 1 MM PITCH, PLASTIC, LBGA-256
文件页数: 133/193页
文件大小: 10683K
代理商: PEF22508E
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页当前第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页
OctalLIU
TM
PEF 22508 E
Functional Description
Data Sheet
44
Rev. 1.0, 2005-06-02
n: even address
3.5.2
Serial Micro Controller Interfaces
Two serial interfaces are included to enable device programming and controlling:- Slave Serial Control Interface
(SCI) - Slave Serial Peripheral Interface (SPI)
By using the SCI Interface, the OctalLIU
TM can be easily connected to Infineon interworking devices plus Infineon
SHDSL- and ADSL-PHYs so that implementation of different line transmission technologies on the same line card
easily is possible. The SCI interface is a three-wire bus and optionally replaces the parallel processor interface to
reduce wiring overhead on the PCB, especially if multiple devices are used on a single board. Data on the bus is
HDLC encapsulated and uses a message-based communication protocol.
If SCI interface with multipoint to multipoint configuration is used, address pins A(5:0) are used for SCI source
(slave) address pin strapping, see Table 2.
Note that after a reset writing into or reading from OctalLIU
TM registers using the SCI- or SPI-Interface is not
possible until the PLL is locked: If the SCI-Interface is used no acknowledge message will be sent by the
OctalLIU
TM. If the SPI-Interface is used pin SDO has high impedance (SDO is pulled up by external resistor). To
trace if the SPI interface is accessible, the micro controller should poll for example the register DSTR so long as
it read no longer the value F
H .
3.5.2.1
SCI Interface
The Serial Control Interface (SCI) is selected if IM(1:0) is strapped to 11
H.
The OctalLIU
TM SCI interface is always a slave.
Figure 49 shows the timing diagram of the SCI interface, Table 56 gives the appropriate values of the timing
parameters.
Figure 6 shows a first application using the SCI interfaces of some OctalLIU
TMs where point to point full duplex
connections are realized between every OctalLIU
TM and the micro controller. Here the data out pins of the SCI
interfaces (SCI_TXD) of the OctalLIU
TMs must be configured as push-pull (PP), see configuration register bit PP
Figure 7 shows an application with Multipoint to multipoint connections between the OctalLIU
TMs and the micro
controller (half duplex). Here the data out pin of the SCI interfaces (SCI_TXD) of all OctalLIU
TMs must be
configured as an open Drain (oD), see configuration register bit PP in Table 8. The data out and data in pins
(SCI_RXD, SCI_TXD) of each OctalLIU
TM are connected together to form a common data line. Together with a
common pull up resistor for the data line, all open Drain data out pins are building a wired And.
The Infineon proprietary Daisy-Chain approach is not supported
The group address of the SCI interface is 00
H after reset. Recommendation for configuring is C4H to be different
to the group addresses of all other Infineon devices.
In case of multipoint to multipoint applications the 6 MSBs of the SCI source address will be defined by
pinstrapping of the address pins A5 to A0. The two LSBs of the SCI source address are constant 10B, see
Table 8. The SCI source address can be overwritten by a write command into the SCI configuration register. For
applications with point to point connections for the SCI interface the source address is not valid.
Because 14 bits are used for the register addresses in the SCI interface macro the two MSBs of the 16 bit wide
register addresses are set fixed to zero.
Intel
(Address n + 1)
(Address n)
Motorola
(Address n)
(Address n + 1)
Data lines
D15
D8
D7
D0
相关PDF资料
PDF描述
PEF22554E DATACOM, FRAMER, PBGA160
PEF22554HT DATACOM, FRAMER, PQFP144
PES12-42S-N0024
PESD3V3V4UK,132 25 W, UNIDIRECTIONAL, 4 ELEMENT, SILICON, TVS DIODE
PF38F3050L0YUQ3A SPECIALTY MEMORY CIRCUIT, PBGA88
相关代理商/技术参数
参数描述
PEF22508EV1.1-G 功能描述:网络控制器与处理器 IC T/E RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
PEF22508EV11G 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述:
PEF22508EV11GXP 制造商:Lantiq 功能描述:LINE INTERFACE UNITS
PEF22508EV11GXT 制造商:Lantiq 功能描述:LINE INTERFACE UNITS
PEF22509EV1.1 制造商:Infineon Technologies AG 功能描述:SP000205605_T/E ASIC_TY_PB