
Data Sheet
71
Rev. 1.0, 2005-06-02
OctalLIU
TM
PEF 22508 E
Functional Description
3.9
Transmit Path
The transmit path of the OctalLIU
Figure 29
Transmit System of one Channel
The serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following
functions:
AIS generation (blue alarm)
Generation of In-band loop-up/-down code
3.9.1
Transmit Line Interface
The principle transmit line interface is shown in Figure 30. Two application modes are possible:
For non-generic applications pins XL3 and XL4 can be left open. The serial resistance R
SER is dependent on
the operation mode (E1/T1/J1) as shown in Table 23.
For generic E1/T1/J1 applications with optimized return loss the transmit output resistance is configured by
using the pins XL3 and XL4 as shown in Figure 30. The operation mode (E1/T1/J1) is selected by software
(register bit PC6.TSRE) without the need for external hardware changes: Here R
SER is always 2 , see
In E1 mode the value of R
SER in Table 23 is valid for both characteristic line impedances Z0 = 120 and Z0 = 75 . Shorts between XL1 and XL2 cannot be detected, see Chapter 3.9.7.
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the
appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter.
Pulse
Shaper,
LBO
Encoder
XDIP
XCLK
XL2
DCO-X
Dual Transmit Elastic Buffer
MCLK
OctalLIU_ITS10305
Transmit Line
Interface
E: controlledby CMR2.IXSC andCMR2.IRSC
F: controlledby CMR1.DXSSandautomatic transmit clock switching
G: controlledby LIM1.RL,JATT andLIM2.ELT
H: controlledby DIC1.XBS(1:0) andautomatic transmit clock switching
%: divider: controlledby CMR6.STF(2:0)
Master
Clocking Unit
DAC
XL1/XOID
G
H
E
F
%
FCLKR
TCLK
FCLKX
Automatic Transmit
Clock Switching
recovered
receive clock
internal
transmit
clock
from
DCO-R
(in)
XL4
XL3
XDIN