
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
166
11.5 TC Layer Registers
Register 0x060: TTTC Indirect Link Control Register
Bit
Type
Function
Default
15
R
LBUSY
0
14
R/W
LRWB
0
13:7
Unused
0
6:5
R/W
SPE[1:0]
0
4:0
R/W
LINK[4:0]
0
This register provides the link number used to access the TTTC link provision
RAM. Writing to this register triggers an indirect link register access.
LINK[4:0],SPE[1:0]:
LINK[4:0] and SPE[1:0] are used to specify the link to be configured or
interrogated in the indirect link access.
SBI mode: Valid values for SPE are 0x1 to 0x3, and valid values for LINK are
0x1 to 0x1C.
Clk/Data mode: SPE and LINK are combined to form the Virtual Link number.
84 virtual links are available. Valid values for the SPE/LINK fields are 0x00 to
0x53.
LRWB:
The link indirect access control bit (LRWB) selects between either a configure
(write) or interrogate (read) access to the link-context RAM. Writing a logic 0
to LRWB triggers an indirect write operation. Data to be written is taken from
the Indirect Link Data registers. Writing a logic 1 to LRWB triggers an indirect
read operation. The read data can be found in the Indirect Link Data registers.
LBUSY:
The indirect link access status bit (LBUSY) reports the progress of an indirect
access A write to the Indirect Link Address register triggers an indirect access
and sets LBUSY to logic 1; it will remain logic 1 until the access is complete.
This register should be polled to determine either: (1) when data from an
indirect read operation is available in the Indirect Link Data registers or (2)