
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
201
Register 0x0E4: SBI Insert Master Interrupt Register
Bit
Type
Function
Default
15:6
Unused
0
5
RO
DCR_INTI_SHDW
0
4
RSVD
Unused
0
3
RO
FIFO_UDRI_SHDW
0
2
RO
FIFO_OVRI_SHDW
0
1
R2C
SBIIP_SYNC_INTI
0
0
R2C
C1FP_SYNC_INTI
0
C1FP_SYNC_INTI
This bit is set when a C1FP realignment has been detected.
SBIIP_SYNC_INTI
This bit is set when a SBIIP_SYNC realignment has been detected. This
generally happens when the SBI interface is configured and indicates an
internal bus sync event. After configuration, this interrupt should not occur.
FIFO_OVRI_SHDW
This bit is a shadow of the FIFO_OVRI bit in the SBI Insert FIFO Over Run
Interrupt Status Register. It is set when the FIFO_OVRI bit is set and the
interrupt enable FIFO_OVRE is set. Reading this register has no affect on the
interrupt status.
FIFO_UDRI_SHDW
This bit is a shadow of the FIFO_UDRI bit in the SBI Insert FIFO Under Run
Interrupt Status Register. It is set when the FIFO_UDRI bit is set and the
interrupt enable FIFO_UDRE is set. Reading this register has no affect on the
interrupt status.
DCR_INTI_SHDW
This bit is a shadow of the DCR_INTI bit in the SBI Insert Depth Check
Interrupt Status Register. It is set when the DCR_INTI bit is set and the
interrupt enable DCR_INT_EN is set. Reading this register has no affect on
the interrupt status.