
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
353
FIFO overrun/underrun errors are reported by indicating error status in
the Extract/Insert FIFO Underrun/Overrun Interrupt Status Register
with the failing link identified.
These interrupts can only be cleared by reading the FIFO
overrun/underrun register with the failing link. Only one error can be
reported at a time. However errors are latched internally so that if
multiple errors occur, any pending errors will be reported when the first
one is cleared.
If the ALM bit in the SBI V4 byte is detected to be changed on a
particular tributary, then the corresponding SPEx_ALRM_INT bit is set
in the SBI Extract Alarm Interrupt Register. The SPEx_ALRM_STAT bit
associated with that tributary indicates the current state of the Extract
SBI ALARM on the SBI tributary.
This SBI_ALRM_INTn interrupt can be cleared only by reading the SBI
Extract Alarm Interrupt register.
12.3.1.1
Programming Sequence for SBI
To have a clean start up, the following programming sequences are
recommended when setting up the SBI interface:
General rules:
All INSBI/EXSBI read and write accesses must wait until the bistinit_done
bit is set after chip SW_RESET is cleared, to allow time for the
INSBI/EXSBI to complete self-initialization. Other general control register
outside of INSBI/EXSBI can be configured at any time.
At initialization, on the SBI Drop bus, the SBI tributary receiver should be
enabled before the corresponding SBI tributary transmitter (i.e.,
configuring EXSBI before INSBI). The same applies for the SBI Add bus.
Following a configuration change, which generates a Configuration Reset,
a tributary may not become active for up to 1 ms following the change.
Any write to a Tributary Control register for a tributary will generate a
configuration reset on that tributary, irrespective of whether the data
written to the tributary control register is unchanged from the previous
value.