
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
169
Register 0x070: RTTC Indirect Link Control Register
Bit
Type
Function
Default
15
R
LBUSY
0
14
R/W
LRWB
0
13
R/W
DRHCSE
0
12:7
Unused
0
6:5
R/W
SPE[1:0]
0
4:0
R/W
LINK[4:0]
0
This register provides the link number used to access the RTTC link provision
RAM. Writing to this register triggers an indirect link-register access.
LINK[4:0],SPE[1:0]:
LINK[4:0] and SPE[1:0] are used to specify the link to be configured or
interrogated in the indirect link access.
SBI mode: Valid values for SPE are 0x1 to 0x3, and valid values for LINK are
0x1 to 0x1C.
Clk/Data mode: SPE and LINK are combined to form the Virtual Link number.
84 virtual links are available. Valid values for the SPE/LINK fields are 0x00 to
0x53.
DRHCSE:
Disable Reset of the HCS Error Count (DRHCSE) disables automatic reset of
the HCS Error Counter (HCSERR). When the bit is set to logic 0, automatic
reset of the HCS Error Counter is enabled. If an indirect read is initiated (i.e.,
CRWBs written with logic 1) with DRHCSE logic 0, the HCS Error Counter is
reset to zero upon completion of the indirect read. When the DRHCSE bit is
set to logic 1, automatic reset of the HCS Error Counter is disabled.
An indirect read results in the interrupt status, as well as the HCSERR count,
being read (and possibly cleared). In this situation, the DRHCSE bit is useful
for separating interrupt processing from HCSERR count accumulation
because it can disable the HCSERR count reset when querying for interrupts.