
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
34
Figure 2
- ATM Multiservice Switch, Any Service Any Port Card Example
OC-12
STS-12
SONET/SDH
Framer
Telecom
T1/J1/E1 Framer
TU/VT Mapper
M13 Mux
SBI
Packet
Processor
AAL1 Circuit
Emulation Service
Voice Processor
Any-PHY
UTOPIA L2 /
Any-PHY
OAM and
Policing
Traffic
Manager
H-MVIP
PM5313
SPECTRA-
622
RM7000
MIPS
Processor
DSP
PM73122
AAL1gator-32
PM7341
S/UNI-IMA-84
PM7389
FREEDM-84
Packet/Cell
Internetworking
Function
A
U
PM7324
S/UNI-ATLAS
PM7326
S/UNI-APEX
VoATM
Voice Processing
Circuit
Emulation Service
ML-PPP and
ML-Frame Relay
IMA / UNI
PM8316
TEMUX-84
PM8316
TEMUX-84
PM8316
TEMUX-84
PM8316
TEMUX-84
IMA / UNI
The S/UNI-IMA-84 implements the IMA 1.1 protocol (with backward compatibility
to IMA 1.0) including link and group state machines, HEC cell delineation (UNI),
cell scheduling and provides internal cell FIFOs. The S/UNI-IMA-84 interfaces
seamlessly over a standard UTOPIA Level 2 or Any-PHY bus to an ATM Traffic
Management device such as the PM7326 S/UNI-APEX. Depending on the
S/UNI-IMA-84’s register configuration, ATM traffic is sent over the network as part
of an IMA 1.1 or IMA 1.0 group or over a standard ATM over T1/E1 or DS3 UNI.
Through register programming, for example, the number of links, groups,
minimum and maximum number of links/group, frame sizes (M=32, 64, 128,
256), differential delay tolerance, transmit clock mode (independent and
common) and symmetrical/asymmetrical configuration and operation are
dynamically configurable. An external low-cost standard 4Mx16 SDRAM is
required to buffer data for tolerating up to a maximum of 279 msec (T1) / 226
msec (E1) of differential delay across the links.