
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
197
Register 0x0C8: SBI Insert Tributary Control RAM Indirect Access Control
Register
Bit
Type
Function
Default
15:8
Unused
0
7
RO
BUSY
0
6
R2C
HST_ADDR_ERR
0
5:2
Unused
0
1
R/W
RWB
0
0
R/W
Reserved
0
RWB
The indirect access control bit (RWB) selects between a configure (write) or
interrogate (read) access to the control configuration RAM. Writing a ‘0’ to
RWB triggers an indirect write operation. Data to be written is taken from the
SBI Insert Tributary Control Indirect Access Data Register. Writing a ‘1’ to
RWB triggers an indirect read operation. The data read can be found in the
SBI Insert Tributary Control Indirect Access Data Register.
HST_ADDR_ERR
When set following a host read, this bit indicates that an illegal host access
was attempted. An illegal host access occurs when an attempt is made to
access an out-of-range tributary.
BUSY
The indirect access status bit (BUSY) reports the progress of an indirect
access. BUSY is set high when a write to the SBI Insert Tributary RAM
Indirect Access Control Register triggers an indirect access and will stay high
until the access is complete. This register should be polled to determine
either: (1) when data from an indirect read operation is available in the
Indirect Tributary Data register or (2) to determine when a new indirect write
operation may commence.