
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
44
9.2 Receive Slave ATM Interface (UTOPIA L2 mode) (26 Signals)
Pin Name
Type
Pin
No.
Function
RCLK
Input
W24
The
Receive Clock
(RCLK) signal is used to
transfer data blocks from the S/UNI-IMA-84 across
the receive UTOPIA L2 interface.
The RCA, RSOC, RDAT[15:0], and RPRTY outputs
are updated on the rising edge of RCLK. The RENB
and RADR[4:0] inputs are sampled on the rising
edge of RCLK.
The RCLK input must cycle at a 52 MHz or lower
instantaneous rate.
RCA
Tristate
Output
AB24
The
Receive Cell Available
(RCA) is an active high
signal that, when polled using the RADR[4:0]
signals, indicates if at least one cell is queued for
transfer on the selected logical channel FIFO .
The S/UNI-IMA-84 device drives RCA with the cell
availability status for the polled port one RCLK cycle
after a valid RADR[4:0] address is sampled. The
RCA output is high-impedance at all other times.
The RCA output is updated on the rising edge of
RCLK.
RENB
Input
AB26
The
Receive Enable Bar
(RENB) is an active low
signal used to initiate the transfer of cells from the
S/UNI-IMA-84 to an ATM-layer component, such as
a traffic management device.
The RENB input is sampled on the rising edge of
RCLK.
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
Input
AA25
AA23
AA24
AA26
Y25
The
Receive Address
(RADR[4:0]) signals are
used to address the S/UNI-IMA-84 device for the
purposes of polling and selecting for cell transfer.
The RADR[4:0] input bus is sampled on the rising
edge of RCLK.