
PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7341 S/UNI-IMA-84
DATASHEET
PMC-2000223
ISSUE 4
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
56
9.7 Clk/Data (129 signals)
Pin Name
Type
Pin No.
Function
TSCLK[31]
TSCLK[30]
TSCLK[29]
TSCLK[28]
TSCLK[27]
TSCLK[26]
TSCLK[25]
TSCLK[24]
TSCLK[23]
TSCLK[22]
TSCLK[21]
TSCLK[20]
TSCLK[19]
TSCLK[18]
TSCLK[17]
TSCLK[16]
TSCLK[15]
TSCLK[14]
TSCLK[13]
TSCLK[12]
TSCLK[11]
TSCLK[10]
TSCLK[9]
TSCLK[8]
TSCLK[7]
TSCLK[6]
TSCLK[5]
TSCLK[4]
TSCLK[3]
TSCLK[2]
TSCLK[1]
TSCLK[0]
Input
A23
B22
D22
C22
A21
B20
A20
C20
B9
C10
A9
B8
C9
B7
D8
A7
C8
B6
D6
A6
B3
C4
A3
A2
E3
F2
F4
F3
F1
G2
G1
G3
The
Transmit Serial Clock
(TSCLK[31:0])
signals contain the transmit clocks for the 32
independently timed links. The TSDATA[31:0]
signals are updated on the falling edge of the
corresponding TSCLK[31:0] clock.
For channelized T1 or E1 links, TSCLK[n] must
be gapped during the framing bit (for T1
interfaces) or during time-slot 0 (for E1
interfaces) of the TSDATA[n] stream. The S/UNI-
IMA-84 uses the gapping information to
determine the time-slot alignment in the transmit
stream.
For unchannelized links, TSCLK[n] must be
externally gapped during the bits or time-slots
that are not part of the transmission format
payload (i.e., not part of the ATM Cell).
The TSCLK[31:0] input signal is nominally a 50%
duty cycle clock of 1.544 MHz for T1 links and
2.048 MHz for E1 links.
The TSCLK[31:0] may operate at higher rates in
the unchannelized mode. At higher rates, the
amount of lines available is limited. See 12.3.2.2
for more details.