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参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 17/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100
24
Figure 18: Logic Cell Flip-Flop Timings—First Waveform
Table 25: Logic Cell Delays
Symbol
Parameter
Commercial
Industrial
Min.
Max.
Min.
Max.
t
PD
Combinatorial delay of the longest path: time taken by
the combinatorial circuit to output
0.32 ns
0.59 ns
0.34 ns
0.62 ns
tSU
Setup time: time the synchronous input of the flip-flop
must be stable before the active clock edge
0.23 ns
0.56 ns
0.24 ns
0.58 ns
tHL
Hold time: time the synchronous input of the flip-flop
must be stable after the active clock edge
0 ns
N/A
0 ns
N/A
t
ESU
Enable setup time: time the enable input of the flip-flop
must be stable before the active clock edge
0.23 ns
0.85 ns
0.89 ns
0.24 ns
tEHL
Enable hold time: time the enable input of the flip-flop
must be stable after the active clock edge
0 ns
tCO
Clock-to-out delay: the amount of time taken by the flip-
flop to output after the active clock edge.
0.48 ns
0.52 ns
0.50 ns
0.55 ns
t
CWHI
Clock high time: required minimum time the clock stays
high
0.46 ns
tCWLO
Clock low time: required minimum time that the clock
stays low
0.46 ns
tSET
Set delay: time between when the flip-flop is “set” (high)
and when the output is consequently “set” (high)
0.60 ns
0.61 ns
t
RESET
Reset delay: time between when the flip-flop is “reset”
(low) and when the output is consequently “reset” (low)
0.68 ns
0.71 ns
t
SW
Set width: time that the SET signal must remain high/low
0.30 ns
tRW
Reset width: time that the RESET signal must remain
high/low
0.30 ns
t
RESET
t
SW
t
RW
t
SET
CLK
QST
(set)
QRT
(reset)
Q
t
CWHI (min)
t
CWLO (min)
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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