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参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 9/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
17
With bi-directional I/O pins and global clock input pins, the PolarPro device maximizes I/O performance,
functionality, and flexibility. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the
specific I/O standard selected. For single-ended I/O standards, the corresponding VCCIO bank input specifies
the input tolerance and the output drive voltage. Drive strength and slew rate are configured for an entire bank.
Weak keeper, pull-up, and pull-down functions can be configured for individual I/O. The default configuration
for QuickLogic QuickWorks software has the drive strength set to 4 and the slew rate set to wow.
Table 17: GPIO Interface Signals
Signal Name
Direction
Function
Routable Signals
OUTZ
I
Data out from internal logic
OUTRZ_EN
I
Enable for registered OUTZ
OEZ
I
Tristate enable for the output signal
INZ
O
Input signal to the internal logic
INRZ_EN
I
Enable for registered INZ
RST
I
Reset for optional registers
CLK
I
Clock signal for optional registers
DI_EN
I
Enable for I/O input signal. Drives a 1 to internal
logic when disabled.
Static Signals
SLEW[1:0]
I
2-bit slew rate control
P[3:0]
I
Programmable drive strength
OSEL
I
Select signal for registered or flow through OUTZ
ESEL
I
Select signal for registered or flow-through OEZ
ISEL
I
Select signal for registered or flow-through INZ
FIXHOLD
I
Enable control for I/O input delay for hold fixing
PBE
I
Input signals for the weak keeper, pull-up/pull-down
controller, see
Table 18 for functional behavior
PBD
I
PBK
I
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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