- 您现在的位置：买卖IC网 > PDF目录296935 > QL1P100-7PUN86C (QUICKLOGIC CORP) FPGA, 640 CLBS, 100000 GATES, PBGA86 PDF资料下载
参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 2/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100
10
Figure 7: FIFO Flush from PUSH Side
Figure 8 illustrates a POP flush operation. After the Fifo_Pop_Flush is asserted at 2 (POP_Clk), four PUSH
clock cycles (12 through 15) are required to update the POP_FLAG, and PUSH_FLAG signals. The
Almost_Empty signal is asserted to indicate that the pop flush operation has been completed. On the
following rising edge of the POP_Clk (8), the POP_FLAG is updated accordingly to reflect the successful flush
operation.
Figure 8: FIFO Flush from POP Side
Figure 7 and Figure 8 are only true for this particular PUSH-POP clock frequency combination. The clock
frequency and phase difference between POP_Clk and PUSH_Clk can cause an additional flush delay of one
clock cycle in either domain because of the asynchronous relationship between the two clocks.
PUSH_Clk
Fifo_Push_Flush
POP_Clk
Almost_Full
PUSH_FLAG
valid
Almost_Empty
POP_FLAG
0000 (Empty)
earliest PUSH
valid
1
2
3
456
8
79
10
11
12
13
14
15
16
invalid
PO P_C lk
Fifo _P o p _F lush
PUSH_ C lk
Alm o st_E m p ty
PO P_F LA G
0000 (E m p ty)
A lm o st_Full
PUSH_ FL A G
va lid
inva lid
va lid
valid
ea rlie st PU SH
in valid
1
10
2
345
6
7
8
9
11
12
13
14
15
16
inva lid
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
发布紧急采购，3分钟左右您将得到回复。