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参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 29/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
35
Table 36:
I/O Input Register Cell Timing
Symbol
Parameter
Commercial
Industrial
Min.
Max.
Min.
Max.
t
ISU
Input register setup time: time the synchronous input of
the flip-flop must be stable before the active clock edge
2.51 ns
2.85 ns
2.80 ns
2.82 ns
tIHL
Input register hold time: time the synchronous input of
the flip-flop must be stable after the active clock edge
0 ns
tICO
Input register clock-to-out: time taken by the flip-flop to
output after the active clock edge
1.68 ns
2.66 ns
1.58 ns
2.70 ns
tIRST
Input register reset delay: time between when the flip-
flop is “reset” (low) and when the output is consequently
“reset” (low)
1.59 ns
1.53 ns
tIESU
Input register clock enable setup time: time INRZ_EN
must be stable before the active clock edge
0.25 ns
0.40 ns
0.23 ns
0.43 ns
t
IEH
Input register clock enable hold time: time INRZ_EN
must be stable after the active clock edge
0 ns
tIDIENSU
Input data enable setup time: time DI_EN must be stable
before the active clock edge
2.39 ns
5.38 ns
2.28 ns
5.63 ns
tIDIENH
Input data enable hold time: time DI_EN must be stable
after the active clock edge
0 ns
t
IFHSU
Input fixhold setup time: time FIXHOLD must be stable
before the active clock edge
2.39 ns
5.38 ns
2.28 ns
5.63 ns
tIFHH
Input fixhold hold time: time FIXHOLD must be stable
after the active clock edge
0 ns
Table 37: I/O Input Buffer Delays
Symbol
Parameter
Value
To get the total input delay add this delay to tISU
Min.
Max.
t
SID (LVTTL)
LVTTL input delay: Low Voltage TTL for 3.3 V applications
TBD
t
SID (LVCMOS2)
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications
TBD
t
SID (LVCMOS18)
LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications
TBD
t
SID (GTL+)
GTL+ input delay: Gunning Transceiver Logic
TBD
tSID (SSTL3)
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
TBD
t
SID (SSTL2)
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
TBD
t
SID (PCI)
PCI input delay: Peripheral Component Interconnect for 3.3 V
TBD
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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