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| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 44/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
9
FIFO Flush Procedure
When a flush is triggered from one side of the FIFO, the signal propagates and re-synchronizes internally to
the other clock domain. During a flush operation, the values of the FIFO flags are invalid for a specific number
As shown in Figure 7, when the Fifo_Push_Flush asserts, the Almost_Full and PUSH_FLAG signals
become invalid until the FIFO can flush the data with regards to the Push clock domain as well as the Pop clock
domain. After the Fifo_Push_Flush is asserted, the next rising edge of the Pop clock starts the Pop flush
routine.
Figure 7 illustrates a FIFO Flush operation. After the Fifo_Push_Flush is asserted at 2 (PUSH_Clk), four
POP clock cycles (12 through 15) are required to update the POP_FLAG, and PUSH_FLAG signals. The
Almost_Empty signal is asserted to indicate that the push flush operation has been completed. On the
following rising edge of the PUSH_Clk (8), the PUSH_FLAG is accordingly updated to reflect the successful
flush operation.
Table 10: FIFO POP Level Interface Signals
Value
Status
0000
Empty
0001
1 entry in FIFO
0010
2 entries in FIFO
0011
3 entries in FIFO
0100
4 entries in FIFO
0101
5 entries in FIFO
0110
6 entries in FIFO
0111
7 entries in FIFO
1000
8 or more entries in FIFO
1101
One-forth or more full
1110
One-half or more full
1111
Full
Others
Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
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| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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