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参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 6/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100
14
CCM Signals
Table 12 provides the name, direction, function and description of the CCM ports.
Table 13, Table 14 and Table 15 give the values used to configure the Set Mode, Phase Shift Control and
Time Delay Control bits.
Table 12: CCM Signals
Signal Name
Direction
Function
Description
Routable Ports
ded_in
I
Dedicated Input
Clock pad CCM input source.
ded_fd
I
Dedicated Feedback
Automatically calculated and routed by the software tools.
rst_in
I
Reset
Active high reset: If rst_in is asserted, pllout0 and pllout1
are reset to 0. This signal must be asserted and then
released for lock_out to assert.
pllout0
O
0° Phase Clock
0° phase clock output.
pllout1
O
Configurable Phase
Clock
0°, 90°,180°, or 270° phase clock output with programmable
delay.
lock_out
O
Lock Detect
Active high lock detection signal. Active when the pllout
signals correctly output the configured functionality.
Static Ports
fc[1:0]
I
Phase Shift Control
Determines whether pllout1 is 0°, 90°, 180°, or 270°
degrees out of phase with pllout0a.
a. The pllout1 output can vary up to -5% with respect to the pllout0 output. Therefore, QuickLogic recommends thorough post-layout
simulation in order to verify satisfactory operation of the CCMs.
s[1:0]
I
Set Mode
Determines pllout1 and pllout0 frequency multiplier (x1, x2,
or x4).
tdctl[3:0]
I
Time Delay Control
Pllout1 programmable delay, configurable in 250 ps
increments up to a maximum of 2.5 ns.
NOTE: 250 ps can vary depending on process variation.
Table 13: Set Mode Values
s[1:0]
Multiplier
00
x1
01
x2
10
x4
11
Reserved
Table 14: Phase Shift Control Values
fc[1:0]
Phase Shift
(Deg.)
00
0
01
90
10
180
11
270
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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