参数资料
型号: QL1P100-7PUN86C
厂商: QUICKLOGIC CORP
元件分类: FPGA
英文描述: FPGA, 640 CLBS, 100000 GATES, PBGA86
封装: 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86
文件页数: 40/44页
文件大小: 1101K
代理商: QL1P100-7PUN86C
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
5
Figure 4: Horizontal and Vertical Concatenation Examples
Table 3 shows the various RAM configurations supported by the PolarPro RAM modules.
True Dual-Port RAM
PolarPro dual-port RAM modules can also be concatenated to generate true dual-port RAMs. The true dual-
port RAM module’s Port1 and Port2 have completely independent read and write ports, and separate read
and write clocks. This allows Port1 and Port2 to have different data widths and clock domains. It is important
to note that there is no circuitry preventing a write and read operation to the same address space at the same
time. Therefore, it is up to the designer to ensure that the same address is not read from and written to
simultaneously, otherwise the data is considered invalid. Likewise, the same address must not be written to
from both ports at the same time. However, it is possible to read from the same address. Figure 5 shows an
example of a 512x18 true dual-port RAM.
Table 3: Available Dual-Port RAM Configurations
Device
Number of
RAM Blocks
Depth
Width
QL1P100
1
256
1-18
1
512
1-9
2
256
1-36
2
512
1-18
2
1024
1-9
256x36 Dual-Port RAM
RD[35:0]
Horizontal Concatenation
512x18 Dual-Port RAM
Vertical Concatenation
WD[35:0]
WA[8:0]
WEN[3:0]
WD_SEL
WCLK
RA[8:0]
RD_SEL
RCLK
WD[17:0]
WA[8:0]
WEN[1:0]
WD_SEL
WCLK
RA[8:0]
RD_SEL
RCLK
RD[17:0]
相关PDF资料
PDF描述
QL1P100-7PUN86I FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-7PUN86M FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-8PU86C FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-8PU86M FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-8PUN86C FPGA, 640 CLBS, 100000 GATES, PBGA86
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