- 您现在的位置：买卖IC网 > PDF目录296935 > QL1P100-7PUN86C (QUICKLOGIC CORP) FPGA, 640 CLBS, 100000 GATES, PBGA86 PDF资料下载
参数资料
| 型号： | QL1P100-7PUN86C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封装： | 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86 |
| 文件页数： | 5/44页 |
| 文件大小： | 1101K |
| 代理商： | QL1P100-7PUN86C |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
13
Configurable Clock
Manager (CCM)
The CCM features include:
Input frequency range from 10 MHz to 200 MHz
Output frequency range from 25 MHz to 200 MHz
Output jitter is less than 200 ps peak-to-peak
Two outputs: pullout0 (with 0° phase shift), and pullout1 (with an option of 0°, 90°, 180°, or 270° phase
shift plus a programmable delay).
Programmable delay allows delays up to 2.5 ns at 250 ps intervals
Fixed feedback path
Output frequency lock time in less than 10 s
Figure 12: Configurable Clock Manager
The reset signal can be routed from a clock pad or generated using internal logic. The lock_out signal can be
routed to internal logic and/or an output pad. CCM clock outputs can drive the global clock networks, as well
as any general purpose I/O pin. Once the CCM has synchronized the output clock to the incoming clock, the
lock_out signal will be asserted to indicate that the output clock is valid. Lock detection requires at least 10 s
after reset to assert lock_out. The PolarPro CCMs have three modes of operation, based on the input
frequency and desired output frequency. Table 11 indicates the features of each mode.
Table 11: CCM PLL Mode Frequencies
Output
Frequency
Input Frequency
Range
Output Frequency
Range
PLL Mode
x1
25 MHz to 200 MHz
PLL_MULT1
x2
15 MHz to 100 MHz
30 MHz to 200 MHz
PLL_MULT2
x4
10 MHz to 50 MHz
40 MHz to 200 MHz
PLL_MULT4
pllout0
ded_in
pgm_in
fin_cnt
ded_fd
pgm_fd
fd_cnt
rst_in
fc[1:0]
s[1:0]
tdctl[3:0]
pllout1
lock_out
相关PDF资料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL-1RED | 制造商:Panduit Corp 功能描述: |
| QL-1WHT | 制造商:Panduit Corp 功能描述: |
| QL-1YEL | 制造商:Panduit Corp 功能描述:B-SI |
| QL2003 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2003-0PF100C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
发布紧急采购，3分钟左右您将得到回复。