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6 Blocks description
SPEAR-07-NC03
6.3.5
Operational Registers Mapping
Table 12.
USB Host Controller Operational Register Map
Address
Register Name
Description
0x3000_2C00
HcRevision
Revision field Read only
0x3000_2C04
HcControl
USB Host Controller Operating mode
0x3000_2C08
HcCommandStatus
Used by the Host Controller to receive commands issused by
the Host Controller Driver
0x3000_2C0C
HcInterruptStatus
Register provides status on various events that cause hardware
interrupts
0x3000_2C10
HcInterruptEnable
Register is used to control which events generate a hardware
interrupt
0x3000_2C14
HcInterruptDisable
To clear the corresponding bit in the HcInterruptEnable register
0x3000_2C18
HcHCCA
Register contains the physical address of the Host Controller
Communication Area
0x3000_2C1C
HcPeriodCurrentED
Register contains the physical address of the current
isochronous or Interrupt Endpoint Descriptor
0x3000_2C20
HcControlHeadED
Register contains the physical address of the first Endpoint
Descriptor of the Control list
0x3000_2C24
HcControlCurrentED
Register contains the physical address of the current Endpont
Descriptor of the control list
0x3000_2C28
HcBulkHeadED
Register contains the physical address of the first Endpoint
Descriptor of the Bulk list
0x3000_2C2C
HcBulkCurrentED
Register contains the physical address of the current endpoint
of the Bulk list. As the bulk list will be served in a round-robin
fashion, the endpoints will be ordered according to their
insertion to the list.
0x3000_2C30
HcDoneHead
Contains the physical address of the last completed transfer
descriptor that was added to the Done queue.
0x3000_2C34
HcFmInterval
Register contains a 14-bit value which indicates the bit time
interval in a frame, and a 15-bit value indicating the full speed
maximum packet size that the host controller may carry out.
0x3000_2C38
HcFmRemaining
Register is a 14-bit down counter showing the bit time remaining
in the current frame
0x3000_2C3C
HcFmNumber
Register is a 16-bit counter providein a reference among events
happening in the host controller and the host controller driver
0x3000_2C40
HcPeriodicStart
Register has a 14-bit programmable value which determines
when is the earliest time HC should start processing the
periodic list.
0x3000_2C44
HcLSThreshold
Register contains an 11-bit value used by the host controller to
determine whether to commit to the transfer of a maximum of 8-
byte LS packet before EOF.
0x3000_2C48
HcRhDescriptorA
Register (first of 2) describes the characteristics of the root hub
0x3000_2C4C
HcRhDescriptorB
Register (second of 2) describes the characteristic of the root
hub
0x3000_2C50
HcRhStatus
Register represents the Hub status field (lower word of Dword)
and the Hub Status Change field (upper word of Dword)
0x3000_2C54
HcRhPortStatus[1: NDP]
Register [1:NDP] is used to control and report port events on a
per-port basis.
…“
0x3000_2C54+4*NDP
HcRhPortStatus[NDP]
“