- 您现在的位置：买卖IC网 > PDF目录297425 > SPEAR-07-NC03 (STMICROELECTRONICS) 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 PDF资料下载
参数资料
| 型号： | SPEAR-07-NC03 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA180 |
| 封装： | LEAD FREE, 12 X 12 MM, 1.70 MM HEIGHT, LFBGA-180 |
| 文件页数： | 37/194页 |
| 文件大小： | 1987K |
| 代理商： | SPEAR-07-NC03 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页
Obsolete
Product(s)
- Obsolete
Product(s)
Obsolete
Product(s)
- Obsolete
Product(s)
SPEAR-07-NC03
6 Blocks description
131/194
0: Data byte received (if BTF=1)
1: Data byte transmitted
BUSY
: Bus busy.
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. This
information is still updated when the interface is disabled (PE=0).
0: No communication on the bus
1: Communication ongoing on the bus
BTF
: Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt
generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of
DR register. It is also cleared by hardware when the interface is disabled (PE=0).
–
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event. BTF is
cleared by reading SR1 register followed by writing the next byte in DR register.
–
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte
from DR register. The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
ADSL
: Address matched (Slave mode)
This bit is set by hardware as soon as the received slave address matched with the OAR
register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared
by software reading SR1 register or by hardware when the interface is disabled (PE=0). The
SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
M/SL
: Master/Slave.
This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is
cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
SB
: Start bit (Master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register
followed by writing the address byte in DR register. It is also cleared by hardware when the
interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
相关PDF资料 |
PDF描述 |
|---|---|
| SPG-8650A60KHZ | CRYSTAL OSCILLATOR, CLOCK, 0.06 MHz, CMOS OUTPUT |
| SPL-45-GB-EBZ-CDA | FIBER OPTIC TRANSCEIVER, 1480-1500nm, 1250Mbps(Tx), 1250Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| SPL2F85 | FIBER OPTIC LASER DIODE EMITTER, 840-860nm, PANEL MOUNT, TO-220, FC CONNECTOR |
| SPL2Y81-2S | 808 nm, LASER DIODE |
| SPLC-35-FE-BX-CDFA | FIBER OPTIC TRANSCEIVER, 1260-1360nm, 125Mbps(Tx), 125Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPEAR-09-B042 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPEAr㈢ BASIC ARM 926EJ-S core, customizable logic, large IP portfolio SoC |
| SPEAR-09-H022 | 制造商:STMicroelectronics 功能描述: |
| SPEAR-09-H022_06 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC |
| SPEAR-09-H042 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPEAr⑩ Head200, ARM 926, 200 K customizable eASIC⑩ gates, large IP portfolio SoC |
| SPEAR-09-H122 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:SPEAr⑩ Head600 |
发布紧急采购，3分钟左右您将得到回复。