. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts
SYM53C040 DATA MANUAL VERSION 2.0
2-27
PRELIMINARY
Interrupt Status Register (FE04h)
The bits in this register are set when the corresponding interrupt condition occurs. They
are cleared when the interrupt is cleared by the microcontroller. The register contains
interrupt bits for the two SFF-8067 ports or MPIO3_(1-0); the two programmable timers;
the DMA core; the two-wire serial interfaces; and the SCSI core.
Interrupt Mask Register (FE0Dh)
Clearing the bits in this register masks the interrupts corresponding to the bits in the
Interrupt Status register.
Interrupt Destination Register (FE0Eh)
This register provides the ability to route an interrupt to either of the two external
interrupt inputs of the microcontroller core. The bits correspond to the interrupts in the
Interrupt Status register. Clearing the bit routes the interrupt to external interrupt 0, and
setting the bit routes it to external interrupt 1.
FC02h, bit 2
Monitor Busy
When set, causes an interrupt from the SCSI core
to be generated for an unexpected loss of BSY/.
FC07h (Read register)
Reset Parity/Interrupt
Register
Any read to this register resets the Interrupt
Request Active bit (FC05h bit 4)
FC10h, bit 1
DMA Interrupt Enable
When set, the DMA function will generate an
interrupt whenever the TIP bit (bit 0) transitions
from 1 to 0. This signifies that the transfer
completed normally, or was interrupted.
FC14h, bit 0
DMA Interrupt
This is the interrupt value for the DMA function.
This interrupt will only be enabled if the IEN bit
(bit 1 in register FC10h) is set.
Table 2-5
Register bits for interrupt handling (Continued)
Register bit location
Register or Bit
Name
Function