DMA Register FC10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Register FC10h
4-12
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
DMA Register FC10h
DMA Status (DS)
Read/write
The DMA function in the SYM53C040 provides the capability of transferring up to 256
bytes from memory to the SCSI port or vice-versa. The DMA function is designed to
handshake automatically with the SCSI core, to offload the microcontroller and increase
SCSI throughput. The DS register provides basic control of the DMA function, the DTL
register sets the 8-bit transfer length (1 to 256), and the DSDL and DSDH registers set the
16-bit source or destination address for the data to be transferred. The DMA function does
not provide any additional capability for handling SCSI protocol, so all phase changes and
error conditions must still be handled manually by the microcontroller. The DMA
direction is based solely on the SCSI I/O phase lines.
Bits 7-5 Reserved
Bit 4 IOD (I/O direction)
This status bit will indicate the current DMA direction. This bit is written by the micro-
controller. A high on this bit indicates the DMA is reading bytes from the SCSI core and
writing them to memory. A low on this bit indicates the DMA is reading bytes from
memory and writing them to the SCSI core.
Bit 3 TC (transfer complete)
This read-only status bit will read a 1 following the normal completion of a DMA
transfer.
Bit 2 Reserved
Bit 1 IEN (interrupt enable)
When this bit is set to a 1, the DMA function will generate an interrupt whenever the
TIP bit transitions from a 1 to a 0. This signifies that (1) the transfer completed
normally, or (2) the TIP bit was written to a 0, which manually interrupted the transfer.
Bit 0 TIP (transfer in progress)
When this bit is written to a 1, the DMA function will begin a transfer. The transfer
length is specified in the DTL register (FC11h) and the data source or destination
addresses are specified in the DSDL (FC12h) and DSDH (FC13h) registers. The read
value of this bit will stay 1 until either (1) the transfer completes normally, or (2) this
bit is written to a 0, which can only be done when the DMA is not active. While this bit
is 0, the other status bits in this register will be valid and the DTL register will hold the
remaining transfer count. Conditions for which the SCSI core will interrupt are
Reserved
IOD
TC
RES
IEN
TIP
76543210
Defaults:
000
X
0
X