SYM53C040 DATA MANUAL VERSION 2.0
3-17
PRELIMINARY
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments for SFF-8067 Mode
131/
A9
SEL_5,
DSK_RD/
When PARALLEL_ESI is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to read data. When
Parallel_ESI is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.
Port 1
4 mA open-drain
bidirectional
130/B9
SEL_6,
DSK_WR/
When PARALLEL_ESI is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
Parallel_ESI is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.
Port 1
4 mA open-drain
Bidirectional
129/
C9
PARALLEL_
ESI/
Used to select between the SEL_ID
and the bidirectional interface.
Pull-up resistors on the interface
are 3.3 K
minimum. If this pin is
deasserted, the drive is presented
with SEL-ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol. When it is asserted, the
drive begins the discovery process
and prepares to read or write data.
Port 1
4 mA open-drain
bidirectional
127/
D9
PA0
This pin contains bit 0 of the
physical address of the enclosure.
Port 0
input
126/
B10
PA1
This pin contains bit 1 of the
physical address of the enclosure
Port 0
input
125/
C10
PA2
This pin contains bit 2 of the
physical address of the enclosure
Port 0
input
124/
A11
PA3
This pin contains bit 3 of the
physical address of the enclosure
Port 0
input
119/
D10
PA4
This pin contains bit 4 of the
physical address of the enclosure
Port 0
input
Table 3-7
Pin Assignments for SFF-8067 Mode (Continued)
Pin/
Ball
No.
Signal
Name
Description
8067 Port
Pad
Configuration