System Register FF20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Register FF22h
8-14
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
System Register FF20h
Multi-Purpose I/O Bank 3 Output (MPO3)
Read/write
Bits 7-4 Reserved
Bits 3-0 MPO_3, MPO3_2, MPO3_1, MPO3_0 (Multi-purpose I/O Bank 3 Output)
The values stored in these register bits are driven on the I/O pins MPIO3_0, MPIO3_1,
MPIO3_2, and MPIO3_3 when the corresponding pin enable in register FF21h is set.
System Register FF21h
Multi-Purpose I/O Bank 3 Enable (MPE3)
Read/write
Bits 7-4 Reserved
Bits 3-0 MPE3_3, MPE3_2, MPE3_1, MPE3_0 (Multi-purpose I/O Bank 3 Enable)
These bits control the output enables on the I/O pins MPIO3_0, MPIO3_1, MPIO3_2,
and MPIO3_3. A value of 1 turns on the pin driver, and a value of 0 tri-states the pin.
Because the value in this register powers up to all 0s, the pins will initially be tri-stated
at power-up. These pins also have internal 100
A pulldown resistors, which can be
disabled with the MPPE3 register (FF25h).
When the SPEN bit (bit 1 in register FF05h) is set, the MPIO3_2 pin is mapped to the
TXD serial port function of the microcontroller core, and the MPIO3_3 pin is mapped
to the RXD serial port function of the microcontroller core. When the EIEN bit (bit 0 in
register FF05h) is set, the MPIO3_0 pin is mapped to the EXS0_INT external interrupt
function of the microcontroller core and the MPIO3_1 pin is mapped to the EXS1_INT
external interrupt function of the microcontroller core.
System Register FF22h
Multi-Purpose I/O Bank 3 Input (MPI3)
Read only
Bits 7-4 Reserved
Bits 3-0 MPI3_3, MPI3_2, MPI3_1, MPI3_0 (Multi-purpose I/O Bank 3 Input)
Reserved
MPO_3
MPO_2
MPO_1
MPO_0
76543210
Defaults:
00000000
Reserved
MPE3_3
MPE3_2
MPE3_1
MPE3_0
76543210
Defaults:
00000000
Reserved
MPI3_3
MPI3_2
MPI3_1
MPI3_0
76543210
Defaults:
00000000