Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
124
125
A11
C10
SATN-
SATN+
SCSI ATN signal. In single-ended mode,
the SATN- pin is the single-ended signal
pin, and the SATN+ pin should be
connected as a virtual ground on the
SCSI connector.
Single-Ended
or Low-
Voltage
Differential
SCSI I/O
none
126
127
B10
D9
SDP0-
SDP0+
SCSI low data byte parity signal. In
single-ended mode, the SDP0- pin is the
single-ended signal pin, and the SDP0+
pin should be connected as a virtual
ground on the SCSI connector.
Single-Ended
or Low-
Voltage
Differential
SCSI I/O
none
129,130,
131,132,
134,135,
136,137,
139,140,
141,142,
144,145,
146,147
C9, B9,
A9, D8,
C8, B8,
A8, E8,
B7, A7,
D7, E7,
B6, A6,
C6, D6
SD7-, SD7+,
SD6-, SD6+,
SD5-, SD5+,
SD4-, SD4+,
SD3-, SD3+,
SD2-, SD2+,
SD1-, SD1+,
SD0-, SD0+
SCSI low data byte signals. In single-
ended mode, the SDx- pin is the single-
ended signal pin, and the SDx+ pin
should be connected as a virtual ground
on the SCSI connector.
Single-Ended
or Low-
Voltage
Differential
SCSI I/O
none
Table 3-5
JTAG Signal Pins
Pin
Number
BGA
Ball
Number
Pin
Name
Description
Pad Type
Internal
Resistor
91
J13
TCK
Test Clock. The Test Clock pin provides
clocking for the JTAG test logic and
boundary scan.
5V-
tolerant
TTL input
100
A
pullup
90
J12
TMS
Test Mode Select. The Test Mode Select
pin receives a signal to control the
JTAG test operations and boundary
scans.
5V-
tolerant
TTL input
100
A
pullup
Table 3-4
SCSI Pins (Continued)
Pin
Number
BGA Ball
Number
Pin
Name
Description
Pad Type
Internal
Resistor