SYM53C040 DATA MANUAL VERSION 2.0
7-9
PRELIMINARY
Misc. Register FE08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Misc. Register FE09h
Misc. Register FE08h
Timer 1 Final Chain T1FC
Read only
Bits 7-0 T1FC7, T1FC6, T1FC5, T1FC4, T1FC3, T1FC2, T1FC1, T1FC0 (Timer 1 Final
Chain)
These register bits provide the ability to read the final timer 1 divider chain. The timer
expires when the value of this divider chain is equal to the value of the Timer 1
Threshold register (FE06). When this happens, the T1EXP bit (register FE05 bit 7) will
be set and an interrupt will be generated to the microcontroller, through the Interrupt
Status register, if the T1IEN bit (register FE05 bit 0) is set.
Misc. Register FE09h
Timer 2 Control (T2C)
Read/write
Bit 7 T2EXP (Timer 2 expired) (read only)
A value of 1 in the T2EXP bit indicates that the timer has expired and an interrupt has
been generated if the T2IEN bit was set when the timer expired. The interrupt can be
cleared by setting the T2CLR bit.
Bit 6 T2RUN (Timer 2 run)
A value of 1 in the T2RUN bit allows the timer to advance. A value of 0 stops timer
advancement.
Bit 5 T2CLR (Timer 2 clear)
A value of 1 in the T2CLR bit clears the timer. A value of 0 allows the timer to advance
beyond the clear state.
Bit 4 T2PS (Timer 2 pre-scaler)
A value of 1 in the T2PS bit selects the additional divide-by-100 secondary divider
chain, yielding a timer range of .5 ms to 128 ms with a resolution of .5 ms per step (with
a 40 MHz clock). A value of 0 bypasses the secondary divider chain, yielding a timer
range of 5
s to 1.280 ms with a resolution of 5 s per step.
T1FC7
T1FC6
T1FC5
T1FC4
T1FC3
T1FC2
T1FC1
TQFC0
76543210
Defaults:
00000000
T2_EXP
T2RUN
T2CLR
T2PS
RES
T2IEN
76543210
Defaults:
0000
X
0