Misc. Register FE0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Misc. Register FE0Bh
7-10
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
Bit 3-1 Reserved
Bit 0 T2IEN (Timer 2 interrupt enable)
A value of 1 in the T2IEN bit enables the timer’s ability to interrupt the microcontroller
core (through the ISR register) upon expiration. This bit is cleared upon chip reset.
Misc. Register FE0Ah
Timer 2 Threshold (T2T)
Read/write
Bits 7-0 T2TH7, T2TH6, T2TH5, T2TH4, T2TH3, T2TH2, T2TH1, T2TH0 (Timer 2
Threshold)
These register bits select the time-out threshold for timer 2. The 8-bit number
programmed in this register corresponds to a multiple of the selected timer resolution,
which is selected by the T2PS bit (bit 4 of register FE09h). A value of 00h in this register
selects the maximum time-out value of 256 times the selected timer resolution.
Misc. Register FE0Bh
Timer 2 Secondary Chain (T2SC)
Read only
Bit 7 Reserved
Bits 6-0 T2SC6, T2SC5, T2SC4, T2SC3, T2SC2, T2SC1, T2SC0 (Timer 2 Secondary
Chain)
These register bits provide the ability to read the secondary divide-by-100 chain of
timer 2. This chain is enabled with the T2PS bit (bit 4 of register FE09h). When
enabled, a value of 100 decimal in this register triggers advancement of the final timer 1
divider chain.
T2TH7
T2TH6
T2TH5
T2TH4
T2TH3
T2TH2
T2TH1
T2TH0
76543210
Defaults:
00000000
RES
T2SC6
T2SC5
T2SC4
T2SC3
TWSC2
T2SC1
T2SC0
76543210
Defaults:
X
0000000