Two-Wire Register FD04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Register FD04h
6-8
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
2 The last bit received during data transfer. Useful for testing ACK reception from
slave device.
Bit 2 AAS (Addressed As Slave)
When active (1), this bit signifies that an address was received across the Two-Wire Data
register interface that matches the programmed Own Address register setting (Register
FD00h/FD02h, ES0, ES1, ES2 =000). When this bit is cleared, the address matches the
general call address.
Bit 1 LAB (Lost Arbitration Bit)
In a multiple-master environment, if the SYM53C040 loses arbitration to another
master on the bus, then it will relinquish control to the other master and set this bit. It
should be noted that if two masters are simultaneously active on the Data register
interface requesting the exact same operation, then the two masters will not observe
each other and a parallel operation has occurred.
Bit 0 BB_N (Bus Busy)
When active (logic 0), this active low bit signifies that the Data register interface is
currently in use and access is not possible. It is activated upon detection of a start
condition and deactivated upon detection of a stop condition.
Two-Wire Register FD04h
Miscellaneous Register
Read only
Bits 7-1 Reserved
Bit 0 CKSUM (Checksum Error)
This bit is set if an error was detected when checking the checksum value after
download.
Reserved
CKSUM
76543210
Defaults:
00000000