Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-14
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
SFF-8067 Mode
The SFF-8067 interface is enabled when the DIFFSENS pin is tied to VDD. The SCSI pin
functions are reassigned to SFF-8067 port functions as indicated
in Table 3-7 .
Table 3-7
Pin Assignments for SFF-8067 Mode
Pin/
Ball
No.
Signal
Name
Description
8067 Port
Pad
Configuration
147/
D6
SEL_0, D0
When Parallel_ESI is asserted, this
signal contains bit 0 of a data nibble
for read and write operations.
When Parallel_ESI is deasserted,
this signal is the SEL_0 signal,
included for compatibility with
SFF-8045.
Port 0
4 mA open-drain
bidirectional
146/
C6
SEL_1, D1
When Parallel_ESI is asserted, this
signal contains bit 1 of a data nibble
for read and write operations.
When Parallel_ESI is deasserted,
this signal is the SEL_1 signal,
included for compatibility with
SFF-8045.
Port 0
4 mA open-drain
bidirectional
145/
A6
SEL_2, D2
When Parallel_ESI is asserted, this
signal contains bit 2 of a data nibble
for read and write operations.
When Parallel_ESI is deasserted,
this signal is the SEL_2 signal,
included for compatibility with
SFF-8045.
Port 0
4 mA open-drain
bidirectional
144/B6
SEL_3, D3
When Parallel_ESI is asserted, this
signal contains bit 3 of a data nibble
for read and write operations.
When Parallel_ESI is deasserted,
this signal is the SEL_3 signal,
included for compatibility with
SFF-8045.
Port 0
4 mA open-drain
bidirectional