SYM53C040 DATA MANUAL VERSION 2.0
4-13
PRELIMINARY
DMA Register FC11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Register FC12h
DMA Register FC11h
DMA Transfer Length (DTL)
Read/write
Bits 7-0 DTL7, DTL6, DTL5, DTL4, DTL3, DTL2, DTL, DTL0 (Data Transfer Length)
These register bits store the 8-bit transfer length for the DMA function. This register
should be set to a value between 00h and FFh prior to setting bit 0 (TIP) of the DS
register to initiate a transfer. Setting this register to a value of 0 corresponds to a desired
transfer length of 256 bytes. When the transfer ends or is interrupted, this register will
read the value of the number of bytes remaining in the transfer.
DMA Register FC12h
DMA Source/Destination Low (DSDL)
Read/write
Bits 7-0 DSDL7, DSDL6, DSDL5, DSDL4, DSDL3, DSDL2, DSDL1, DSDL0 (DMA
Source/Destination Low)
These register bits store the least significant byte (LSB) of the DMA function’s source
address for send transfers and destination address for receive transfers. The read value
of the DSDL and DSDH registers tracks the current source/destination address of the
transfer. If the transfer is interrupted for any reason, the DSDL and DSDH registers will
hold the next address required, in case the interrupted transfer resumes.
DTL7
DTL6
DTL5
DTL4
DTL3
DTL2
DTL1
DTL0
76543210
Defaults:
00000000
DSDL7
DSDL6
DSDL5
DSDL4
DSDL3
DSDL2
DSDL1
DSDL0
76543210
Defaults:
00000000