SCSI Register FC01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCSI Register FC01h
4-4
SYM53C040 DATA MANUAL VERSION 2.0
PRELIMINARY
SCSI Register FC01h
Initiator Command (ICR)
Read/write
Bit 7 ARST (Assert SRST)
Whenever a 1 is written to this bit, the SRST signal is asserted on the SCSI bus. The
SRST/ signal will remain asserted until this bit is reset or until an external chip reset
occurs. After this bit is set, the IRQ output goes active and all internal logic and control
registers are reset (except for the interrupt latch and the Assert SRST bit). Writing a 0 to
this bit deasserts the SRST signal. Reading this register bit simply reflects the status of
this bit.
Bit 6 AIP (Arbitration In Progress) (read only)
This bit is used to determine if arbitration is in progress. For this bit to be active, the
Arbitrate bit (Mode Register FC02h, bit 0) must have been set previously. It indicates
that a bus free condition has been detected and that the chip has asserted BSY/ and the
contents of the Output Data Register (FC00h) onto the SCSI bus. The AIP bit will
remain active until the Arbitrate bit is reset.
Bit 5 LA (Lost Arbitration)
When active, this read-only bit indicates that the SCSI core has detected a bus free
condition, arbitrated for use of the bus by asserting BSY/ and its ID on the data bus,
and lost arbitration due to SEL/ being asserted by another bus device. For this bit to be
active, the ARB bit (Mode Register FC02h, bit 0) must be active.
Bit 4 AACK (Assert ACK/)
This bit is used by the bus initiator to assert the ACK/ pin on the SCSI bus. In order to
assert ACK/ the Target Mode bit (Mode Register FC02h, bit 6) must be false. Writing a
zero to this bit resets ACK/ on the SCSI bus. Reading this register bit simply reflects the
status of this bit.
Bit 3 ABSY (Assert BSY/)
Writing a 1 into this bit asserts the BSY/ pin onto the SCSI bus. Conversely, a 0 resets
the BSY/ signal. Asserting BSY/ indicates a successful selection or reselection, and
resetting this bit creates a bus disconnect condition. Reading this bit reflects the status
of this bit without changing the value.
Bit 2 ASEL (Assert SEL/)
Writing a 1 into this bit asserts the SEL/ pin onto the SCSI bus. SEL/ is normally
asserted after arbitration has been successfully completed. SEL/ may be deasserted by
resetting this bit to a zero. A read of this register bit simply reflects the status of this bit.
ARST
AIP
LA
AACK
ABSY
ASEL
AATN
ADB
76543210
Defaults:
00000000