SYM53C040 DATA MANUAL VERSION 2.0
4-7
PRELIMINARY
SCSI Register FC03h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCSI Register FC03h
SCSI Register FC03h
Target Command (TC)
Read/write
When connected as a target device, the Target Command register allows the
microcontroller to control the SCSI bus information transfer phase and/or to assert REQ/
simply by writing this register. The Target Mode bit (register FC02h, bit 6) must be set (1)
for bus assertion to occur. When connected as an initiator with DMA Mode true, if the
phase lines (I_O/, C_D/ and MSG/) do not match the phase bits in this register, a phase
mismatch interrupt is generated when REQ/ goes active. In order to send data as an
initiator, the Assert I_O/, Assert C_D/ and Assert MSG/ bits must match the
corresponding bits in the Current SCSI Bus Status Register (FC04h). The Assert REQ/ bit
(bit 3) has no meaning when the SYM53C040 is operating as an initiator.
Bit 7 LBS (Last Byte Sent)
In initiator mode, the SCSI core uses this bit to determine when the last byte of a DMA
transfer is sent to the SCSI bus. This flag is necessary since the End of DMA bit in the
Bus and Status Register only reflects when the last byte was received from the DMA
function.
Bits 6-4 Reserved
Bit 3 AREQ (Assert REQ/)
Bit 2 AMSG (Assert MSG/)
Bit 1 ACD (Assert C_D/)
Bit 0 AIO (Assert I_O/)
These bits, when read together, give the current SCSI bus phas
e. Table 4-2 describes the
SCSI bus phases that correspond to all possible values of these bits.
LBS
RES
AREQ
AMSG
ACD
AIO
76543210
Defaults:
00000000
Table 4-2
SCSI phase bit values
Bus Phase
Assert MSG/
Assert CD/
Assert IO/
Data Out
0
Undefined
100
Command
010
Message Out
1
0
Data In
001
Undefined
101
Status
011
Message In
1