SYM53C040 DATA MANUAL VERSION 2.0
4-5
PRELIMINARY
SCSI Register FC02h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCSI Register FC02h
Bit 1 AATN (Assert ATN/)
The ATN/ pin may be asserted on the SCSI bus by setting this bit to a 1 if the Target
Mode bit (Mode Register FC02h, bit 6) is false. ATN/ is normally asserted by the
initiator to request a Message Out bus phase. Note that since Assert SEL/ and Assert
ATN/ are in the same register, a select with ATN/ may be implemented with one MPU
write. ATN/ may be deasserted by resetting this bit to a 0. A read of this register bit
simply reflects the status of this bit.
Bit 0 ADB (Assert Data Bus)
When set, the Assert Data Bus bit allows the contents of the Output Data Register to be
enabled as chip outputs on the signals DB0/ - DB7/. Parity is also generated and
asserted on DBP/. Resetting this bit disables the output data bus.
When the SYM53C040 is connected as an Initiator, the outputs are only enabled if the
Target Mode bit (Mode Register FC02h, bit 6) is false, the received SCSI I/O signal is
false, and the phase signals (C/D, I/O and MSG) match the contents of the Assert C_D,
Assert I_O/, and Assert MSG/ in the Target Command Register (FC03h).
This bit should also be set during DMA send operations.
SCSI Register FC02h
Mode Register (MR)
Read/write
Bit 7 AS_LVD (Arbitration / Selection LVD)
This bit must be set to perform arbitration, selection, and reselection, and must be
cleared upon successful completion of selection or reselection prior to asserting the
data bus for any information transfer phases. When set this bit causes the SCSI data bus
to operate in open drain mode, which is a requirement of LVD SCSI as defined in the
SPI-2 draft standard. Operation of this bit does not effect SCSI single-ended mode.
Bit 6 TGTM (Target Mode)
The Target Mode bit allows the SCSI core to operate as either a SCSI bus initiator (bit
reset to 0) or as a SCSI bus target device (bit set to 1). In order for the signals ATN/ and
ACK/ to be asserted on the SCSI bus, the Target Mode bit must be reset (0). In order for
the signals C_D/, I_O/, MSG/ and REQ/ to be asserted on the SCSI bus, the Target
Mode bit must be set (1).
Bit 5 EPC (Enable Parity Checking)
The Enable Parity Checking bit determines whether parity errors will be ignored or
saved in the parity error latch. If this bit is reset (0), parity will be ignored. Conversely, if
this bit is set (1), parity errors will be saved.
AS_LVD
TGTM
EPC
EPI
RES
MB
DM
ARB
76543210
Defaults:
00000000