参数资料
型号: TMS320C542PGE-40
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装: PLASTIC, QFP-144
文件页数: 108/111页
文件大小: 1467K
代理商: TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
96
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions for buffered serial port
transmit of internal frame and internal clock [H = 0.5tc(CO)] (see Figure 37)
PARAMETER
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
MAX
MIN
MAX
tc(SCK)
Cycle time, serial port clock, internal clock
2H
62H
20
62H
ns
td(BFSX)
Delay time, BFSX after BCLKX rising edge
(see Notes 3 and 4)
10
ns
td(BDX)
Delay time, BDX valid after BCLKX rising edge
8
ns
tdis(BDX)
Disable time, BDX after BCLKX rising edge
0
5
0
5
ns
tdis(BDX)pcm
Disable time, PCM mode, BDX after BCLKX rising edge
5
ns
ten(BDX)pcm
Enable time, PCM mode, BDX after BCLKX rising edge
7
ns
th(BDX)
Hold time, BDX valid after BCLKX rising edge
0
ns
tf(SCK)
Fall time, serial port clock
4
ns
tr(SCK)
Rise time, serial port clock
4
ns
tw(SCK)
Pulse duration, serial port clock low/high
H–4
6
ns
NOTES:
3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
8/10/12/16
2
1
BDX
BFSX
BCLKX
tc(SCK)
td(BFSX)
tdis(BDX)
tw(SCK)
th(BDX)
td(BDX)
tw(SCK)
tr(SCK)
tf(SCK)
Figure 37. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames
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