参数资料
型号: TMS320C542PGE-40
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装: PLASTIC, QFP-144
文件页数: 52/111页
文件大小: 1467K
代理商: TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
processor-mode status register (PMST)
The processor-mode status register (PMST) controls memory configurations of the ’54x devices.
interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 12.
Table 12. ’54x Interrupt Locations and Priorities
NAME
LOCATION
PRIORITY
FUNCTION
NAME
DECIMAL
HEX
PRIORITY
FUNCTION
RS, SINTR
0
00
1
Reset (Hardware and software reset)
NMI, SINT16
4
04
2
Nonmaskable interrupt
SINT17
8
08
Software interrupt #17
SINT18
12
0C
Software interrupt #18
SINT19
16
10
Software interrupt #19
SINT20
20
14
Software interrupt #20
SINT21
24
18
Software interrupt #21
SINT22
28
1C
Software interrupt #22
SINT23
32
20
Software interrupt #23
SINT24
36
24
Software interrupt #24
SINT25
40
28
Software interrupt #25
SINT26
44
2C
Software interrupt #26
SINT27
48
30
Software interrupt #27
SINT28
52
34
Software interrupt #28
SINT29
56
38
Software interrupt #29
SINT30
60
3C
Software interrupt #30
INT0, SINT0
64
40
3
External user interrupt #0
INT1, SINT1
68
44
4
External user interrupt #1
INT2, SINT2
72
48
5
External user interrupt #2
TINT, SINT3
76
4C
6
External timer interrupt
BRINT0, SINT4
80
50
7
BSP #0 receive interrupt
BXINT0, SINT5
84
54
8
BSP #0 transmit interrupt
TRINT, SINT6
88
58
9
TDM receive interrupt
TRINT, SINT7
92
5C
10
TDM transmit interrupt
INT3, SINT8
96
60
11
External user interrupt #3
HINT, SINT9
100
64§
12
HPI interrupt (’542, ’545, ’548, ’549 only)
BRINT1, SINT10
104
68§
13
BSP #1 receive interrupt (’548, ’549 only)
BXINT1, SINT11
108
6C§
14
BSP #1 transmit interrupt (’548, ’549 only)
BMINT0, SINT12
112
70§
15
BSP #0 misalignment detection interrupt (’549 only)
BMINT1, SINT13
116
74§
16
BSP #1 misalignment detection interrupt (’549 only)
120–127
78–7F§
Reserved
On ’541 devices, these interrupt locations are serial port 0 interrupts (RINT0/XINT0).
On ’541, ’545, and ’546 devices, these interrupt locations are serial port 1 interrupts (RINT1/XINT1).
§ On ’541, ’543, and ’546 devices, interrupt locations 64h – 7Fh are reserved. On ’542 and ’545 devices, interrupt locations 68h – 7Fh are reserved.
On ’548 devices, interrupt locations 70h – 7Fh are reserved.
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