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| 型号： | TMS320C542PGE-40 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 16/111页 |
| 文件大小： | 1467K |
| 代理商： | TMS320C542PGE-40 |
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
’54x Signal Descriptions
TERMINAL
DESCRIPTION
NAME
TYPE
DESCRIPTION
DATA SIGNALS
A22
(MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
O/Z
Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address
external data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0
also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for
extended program memory addressing (’548 and ’549 only).
On the ’548 and ’549 devices, the address bus have a feature called bus holder that eliminates passive
components and the power dissipation associated with it. The bus holders keep the address bus at the previous
logic level when the bus goes into a high-impedance state. The bus holders on the address bus are always
enabled.
D15
(MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
I/O/Z
Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when
not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF
is low.
The data bus has a feature called bus holder that eliminates passive components and the power dissipation
associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a
high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control
register (BSCR).
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when
EMU1/OFF is low.
INT0
INT1
INT2
INT3
I
External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the
interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.
I = Input, O = Output, Z = High impedance
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TMS320C54CST | 制造商:TI 制造商全称:Texas Instruments 功能描述:Client Side Telephony DSP |
| TMS320C54CSTGGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTPGE | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTZGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54V90 | 制造商:TI 制造商全称:Texas Instruments 功能描述:EMBEDDED V.90 MODEM DSP |
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