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参数资料
| 型号： | TMS320C542PGE-40 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 25/111页 |
| 文件大小： | 1467K |
| 代理商： | TMS320C542PGE-40 |
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
bus structure (continued)
The ’548 and ’549 devices also have equivalent bus keepers connected to the address bus. The bus keepers
ensure the address bus does not float when in high-impedance. For the ’548 and ’549 devices, the bus keepers
are always enabled.
Table 2 summarizes the buses used by various types of accesses.
Table 2. Bus Usage for Accesses
ACCESS TYPE
ADDRESS BUS
PROGRAM
BUS
DATA BUS
ACCESS TYPE
PAB
CAB
DAB
EAB
PB
CB
DB
EB
Program read
√
Program write
√
Data single read
√
Data dual read
√
Data long (32-bit) read
√(hw)
√(lw)
√(hw)
√(lw)
Data single write
√
Data read/data write
√
Dual read/coefficient read
√
Peripheral read
√
Peripheral write
√
Legend:
hw = high 16-bit word
lw = low 16-bit word
memory
The total memory address range for the host of ’54x devices is 192K 16-bit words. The ’548 and ’549 devices
have 8M-word program memory. The memory space is divided into three specific memory segments: 64K-word
program, 64K-word data, and 64K-word I / O. The program memory space contains the instructions to be
executed as well as tables used in execution. The data memory space stores data used by the instructions. The
I / O memory space interfaces to external memory-mapped peripherals and can also serve as extra data storage
space.
The parallel nature of the architecture of these DSPs allows them to perform four concurrent memory operations
in any given machine cycle: fetching an instruction, reading two operands, and writing an operand. The four
parallel buses are the program-read bus (PB), the data-write bus (EB) and the two data-read buses (CB and
DB). Each bus accesses different memory spaces for different aspects of the DSP’s operation. Additionally, this
architecture allows dual-operand reads, 32-bit-long word accesses, and a single read with a parallel store.
The ’54x DSPs include on-chip memory to aid in system performance and integration.
on-chip ROM
The ’C541 and ’LC541 feature a 28K-word
× 16-bit on-chip maskable ROM. 8K words of the ’C541 and ’LC541
ROM can be mapped into program and data memory space if the data ROM (DROM) bit in the processor mode
status (PMST) register is set. This allows an instruction to use data stored in the ROM as an operand.
The ’LC545/’LC546 all feature a 48K-word
× 16-bit on-chip maskable ROM. 16K words of the ROM on these
devices can be mapped into program and data memory space if the DROM bit in the PMST register is set.
The ’C542/’LC542/’LC543 / ’LC548 all feature 2K-word
× 16-bit on-chip ROM.
The ’LC549 and ’VC549 feature 16K-word x 16-bit on-chip ROM.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TMS320C54CST | 制造商:TI 制造商全称:Texas Instruments 功能描述:Client Side Telephony DSP |
| TMS320C54CSTGGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTPGE | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTZGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54V90 | 制造商:TI 制造商全称:Texas Instruments 功能描述:EMBEDDED V.90 MODEM DSP |
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