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参数资料
| 型号： | TMS320C542PGE-40 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 41/111页 |
| 文件大小： | 1467K |
| 代理商： | TMS320C542PGE-40 |
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
use of the PLLCOUNT programmable lock timer (continued)
80
60
20
100
70
50
40
30
10
2.5
0
5
10
15
20
25
30
35
40
45
50
55
60
’549 Only
CLKOUT Frequency (MHz)
23
16
17
16
22
44
59
19
24
29
35
Lockup
T
ime
(
s)
Figure 8. PLL Lockup Time Versus CLKOUT Frequency
switching from DIV mode to PLL mode
Several circumstances may require switching from DIV mode to PLL mode; however, note that if the PLL is not
locked when switching from DIV mode to PLL mode, the PLL lockup time delay must be observed before the
mode switch occurs to ensure that only proper clock signals are sent to the device. It is, therefore, important
to know whether or not the PLL is locked when switching operating modes.
The PLL is unlocked on power-up, after changing the PLLMUL or PLLDIV values, after turning off the PLL
(PLLON/OFF = 0), or after loss of input reference clock. Once locked, the PLL remains locked even in DIV mode
as long as the PLL had been previously locked and has not been turned off (PLLON/OFF stays 1), and the
PLLMUL and PLLDIV values have not been changed since the PLL was locked.
Switching from DIV mode to PLL mode (setting PLLNDIV to 1) activates the PLLCOUNT programmable lock
timer (when PLLCOUNT is preloaded with a non-zero value), and this can be used to provide a convenient
method for implementing the lockup time delay. The PLLCOUNT lock timer feature should be used in the
situations described above, where the PLL is unlocked unless a reset delay is used to implement the lockup
delay, or the PLL is not used.
Switching from DIV mode to PLL mode is accomplished by loading the CLKMD register. The following procedure
describes switching from DIV mode to PLL mode when the PLL is not locked. When performing this mode switch
with the PLL already locked, the effect is the same as when switching from PLL to DIV mode, but in the reverse
order. In this case, the delays of when the new clock mode takes effect are the same.
When switching from DIV to PLL mode with the PLL unlocked, or when the mode change will result in unlocked
operation, the PLLMUL[3–0], PLLDIV, and PLLNDIV bits are set to select the desired frequency multiplier as
described in Table 5, and the PLLCOUNT[7–0] bits are set to select the required lockup time delay. Note that
PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF can only be modified when in DIV mode.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TMS320C54CST | 制造商:TI 制造商全称:Texas Instruments 功能描述:Client Side Telephony DSP |
| TMS320C54CSTGGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTPGE | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54CSTZGU | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP for Client-Side Telephony RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| TMS320C54V90 | 制造商:TI 制造商全称:Texas Instruments 功能描述:EMBEDDED V.90 MODEM DSP |
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