参数资料
型号: TMS320C542PGE-40
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装: PLASTIC, QFP-144
文件页数: 72/111页
文件大小: 1467K
代理商: TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
63
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
internal oscillator with external crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device dependent –
see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices
with the software PLL can also be changed to divide-by-four.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 13. The load capacitors, C1 and C2, should be chosen such that the
equation below is satisfied. CL in the equation is the load specified for the crystal.
C
L
+
C
1C2
(
C
1
) C
2)
recommended operating conditions (see Figure 13)
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
fx
Input clock frequency
10
20
10
20
10
20
MHz
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
X1
X2/CLKIN
C1
C2
Crystal
Figure 13. Internal Divide-by-Two Clock Option With External Crystal
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