参数资料
型号: TMS320C542PGE-40
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装: PLASTIC, QFP-144
文件页数: 73/111页
文件大小: 1467K
代理商: TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
64
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
divide-by-two/divide-by-four clock option – PLL disabled
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 13
and Figure 14, and the recommended operating conditions table)
PARAMETER
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tc(CO)
Cycle time, CLKOUT
25
2tc(CI)
20
2tc(CI)
15
2tc(CI)
ns
td(CIH-CO)
Delay time, X2/CLKIN high to
CLKOUT high/low
6
12
18
6
12
18
4
10
16
ns
tf(CO)
Fall time, CLKOUT
2
ns
tr(CO)
Rise time, CLKOUT
2
ns
tw(COL)
Pulse duration, CLKOUT low
H–4
H–2
H
H–4
H–2
H
H–4
H–2
H
ns
tw(COH)
Pulse duration, CLKOUT high
H–4
H–2
H
H–4
H–2
H
H–4
H–2
H
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
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