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参数资料
型号： TMS320C542PGE-40
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装： PLASTIC, QFP-144
文件页数： 109/111页
文件大小： 1467K
代理商： TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
97
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial-port receive timing in TDM mode
timing requirements for serial-port receive in TDM mode [H = 0.5tc(CO)] (’542/’543 only)
(see Figure 38)
’542
’543
UNIT
MIN
MAX
UNIT
tc(SCK)
Cycle time, serial-port clock
8H
ns
tf(SCK)
Fall time, serial-port clock
6
ns
tr(SCK)
Rise time, serial-port clock
6
ns
tw(SCK)
Pulse duration, serial-port clock low/high
4H
ns
tsu(TD-TCL)
Setup time, TDAT/TADD before TCLK falling edge
–(3H–9)
ns
th(TCH-TD)
Hold time, TDAT/TADD after TCLK rising edge, tw(SCKL) < 5H
0
ns
th(TCL-TD)
Hold time, TDAT/TADD after TCLK falling edge, tw(SCKL) > 5H
5H+5
ns
tsu(TF-TCH)
Setup time, TFRM before TCLK rising edge
10
ns
th(TCH-TF)
Hold time, TFRM after TCLK rising edge
10
ns
The serial-port design is fully static and, therefore, can operate with tc(SCK)approachinginfinity.Itischaracterizedapproachinganinputfrequency
of 0 Hz but tested at a much higher frequency to minimize test time.
TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 39.
timing requirements for serial-port receive in TDM mode [H = 0.5tc(CO)] (’54x devices other than
’542/’543) (see Figure 38)
’C54x-40
’LC54x-40
’LC54x-50
’54X-66
UNIT
MIN
MAX
MIN
MAX
tc(SCK)
Cycle time, serial-port clock
8H
16H
ns
tf(SCK)
Fall time, serial-port clock
6
ns
tr(SCK)
Rise time, serial-port clock
6
ns
tw(SCK)
Pulse duration, serial-port clock low/high
4H
8H
ns
tsu(TD-TCH)
Setup time, TDAT/TADD before TCLK rising edge
25
10
ns
th(TCH-TD)
Hold time, TDAT/TADD after TCLK rising edge
–6
1
ns
tsu(TF-TCH)
Setup time, TFRM before TCLK rising edge
10
ns
th(TCH-TF)
Hold time, TFRM after TCLK rising edge
10
ns
The serial-port design is fully static and, therefore, can operate with tc(SCK)approachinginfinity.Itischaracterizedapproachinganinputfrequency
of 0 Hz but tested at a much higher frequency to minimize test time.
TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 39.
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