参数资料
型号: TMS320C542PGE-40
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP144
封装: PLASTIC, QFP-144
文件页数: 5/111页
文件大小: 1467K
代理商: TMS320C542PGE-40
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
102
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
host-port interface timing (continued)
timing requirements for host-port interface [H = 0.5tc(CO)] (see Note 5 and Figure 40 through
Figure 43)
’C54x-40
’C54x-50
’C54x-66
UNIT
MIN
MAX
tsu(HBV-DSL)
Setup time, HAD / HBIL valid before DS or HAS falling edge
10
ns
th(DSL-HBV)
Hold time, HAD / HBIL valid after DS or HAS falling edge
5
ns
tsu(HSL-DSL)
Setup time, HAS low before DS falling edge
12
ns
tw(DSL)
Pulse duration, DS low
30
ns
tw(DSH)
Pulse duration, DS high
10
ns
Cycle time DS rising edge to next DS
Case 1: HOM access timings
(see Access Timing Without HRDY)
50
tc(DSH-DSH)
Cycle time, DS rising edge to next DS
rising edge
Case 2a: SAM accesses and HOM active writes
to DSPINT or HINT.
(see Access Timings With HRDY)
10H
ns
tsu(HDV-DSH)
Setup time, HD valid before DS rising edge
12
ns
td(DSH-HSL)
Delay time, DS high to next HAS low
10H
ns
th(DSH – HDV)W
Hold time, HD valid after DS rising edge, write
3
ns
A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).
NOTE 5: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR / W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
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