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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 11/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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TSPC106A
2102C–HIREL–01/05
Configuration Signals
The configuration signals select the ROM/Flash options, the clock mode of the
TSPC106 and how the TSPC106 responds to addresses on the 60x and PCI buses.
Notes:
1. The TSPC106 samples these signals during a power-on reset or hard reset operation to determine the configuration. Weak
pull-up or pull-down resistors should be used to avoid interference with the normal signal operations.
2. The TSPC106 continuously samples the phase-locked loop (PLL) configuration signals to allow the switching of clock modes
or the bypass of the PLL without a hard reset operation.
Clocking
The TSPC106 requires a single system clock input, SYSCLK. The frequency of
SYSCLK dictates the operating frequency of the PCI bus. An internal PLL on the
TSPC106 generates a master clock that is used for all of the internal (core) logic. The
master clock provides the core frequency reference and is phase-locked to the SYSCLK
input. The 60x processor, L2 cache and memory interfaces operate at the core
frequency.
The PLL[0:3] signals configure the core-to-SYSCLK frequency ratio. The TSPC106 sup-
ports core-to-SYSCLK frequency ratios of 1:1, 2:1 and 3:1, although not all ratios are
supported for all frequencies. The TSPC106 supports changing the clock mode and
bypassing the PLL without requiring a hard reset operation, provided the system design
allows sufficient time for the PLL to relock.
Address Maps
The TSPC106 supports three address mapping configurations designated address map
A, address map B, and emulation mode address map. Address map A conforms to the
“PowerPC Reference Platform Specification”. Address map B conforms to the “Pow-
erPC Common Hardware Reference Platform Architecture (CHRP)”. The emulation
mode address map is provided to support software emulation fx86 hardware. The con-
figuration signal DBG0, sampled during power-on reset, selects between address map
A and address map B. After reset, the address map can be changed by a programmable
parameter. The emulation mode address map can only be selected by software after
reset.
Table 10. Configuration Signals
Signal
Number of Pins
I/O
Configuration
DBG0(1)
1
I
High configures the TSPC106 for address map A.
Low configures the TSPC106 for address map B.
FOE(1)
1
I
High configures ROM bank 0 for an 8-bit data bus width.
Low configures ROM bank 0 for an 64-bit data bus width.
Note that the data bus width for ROM bank 1 is always 64 bits.
PLL[0:3](2)
4
I
High/Low – configuration for the PLL clock mode.
RCS0(1)
1
I
High indicates ROM is located on the 60x processor/memory data bus.
Low indicates ROM is located on the PCI bus.
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