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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 3/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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11
TSPC106A
2102C–HIREL–01/05
DH[0:31],
DL[0:31]
Data bus
64
The data bus is comprised of two halves - data bus high (DH[0:31])
and data bus low (DL[0:31]). The data bus has the following byte lane
assignments:
O
Represents the value of data being driven by the TSPC106.
I
Represents the state of data being driven by a 60x processor, the local
bus slave, the L2 cache or the memory subsystem.
GBL
Global
1
I/O
Indicates that an access is global and hardware needs to enforce
coherency.
LBCLAIM
Local bus slave
cycle claim
1I
Indicates that the local bus slave claims the transaction and is
responsible for driving TA during the data tenure.
MCP
Machine check
1
O
Indicates that the TSPC106 detected a catastrophic error and the 60x
processor should initiate a machine check exception.
TA
Transfer
acknowledge
1
O
Indicates that the data has been latched for a write operation or that
the data is valid for a read operation, thus terminating the current data
beat. If it is the last (or only) data beat, this also terminates the data
tenure.
I
Indicates that the external L2 cache or local bus slave has latched data
for a write operation or is indicating the data is valid for a read
operation. If it is the last (or only) data beat, then the data tenure is
terminated.
TBST
Transfer burst
1
O
Indicates that a burst transfer is in progress.
I
Indicates that a burst transfer is in progress.
TEA
Transfer error
acknowledge
1O
Indicates that a bus error has occurred. Assertion of TEA terminates
the transaction in progress. An unsupported memory transaction, such
as a direct-store access or a graphics read or write, causes the
assertion of TEA (provided TEA is enabled).
TS
Transfer start
1
O
Indicates that the TSPC106 has started a bus transaction and that the
address and transfer attribute signals are valid. Note that the
TSPC106 only initiates a transaction to broadcast the address of a PCI
access to memory for snooping purposes.
I
Indicates that a 60x bus master has begun a transaction and that the
address and transfer attribute signals are valid.
Table 2. 60x Processor Interface Signals (Continued)
Signal
Signal Name
Number of
Pins
I/O
Signal Description
Data Byte
Byte Lane
DH[0:7]
0
DH[8:15]
1
DH[16:23]
2
DH[24:31]
3
DL[0:7]
4
DL[8:15]
5
DL[16:23]
6
DL[24:31]
7
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相关代理商/技术参数 |
参数描述 |
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| TSPC106AVGS83CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGS83CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T66CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T66CG | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
| TSPC106AVGSU/T83CE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MEMORY CONTROLLER |
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