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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 2/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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10
TSPC106A
2102C–HIREL–01/05
60x Processor Interface Signals
Table 2. 60x Processor Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
A[0:31]
Address bus
32
O
Specifies the physical address for 60x bus snooping.
I
Specifies the physical address of the bus transaction. For burst reads,
the address is aligned to the critical double-word address that missed
in the instruction or data cache. For burst writes, the address is aligned
to the double-word address of the cache line being pushed from the
data cache.
AACK
Address
acknowledge
1
O
Indicates that the address tenure of a transaction is terminated. On the
cycle following the assertion of AACK, the bus master releases the
address-tenure-related signals to a high impedance state and samples
ARTRY.
I
Indicates that an externally-controlled L2 cache is terminating the
address tenure. On the cycle following the assertion of AACK, the bus
master releases the address-tenure-related signals to a high
impedance state and samples ARTRY.
ARTRY
Address retry
1
O
Indicates that the initiating 60x bus master must retry the current
address tenure.
I
During a snoop operation, indicates that the 60x either requires the
current address tenure to be retried due to a pipeline collision or needs
to perform a snoop copy-back operation. During normal 60x bus cycles
in a multiprocessor system, indicates that the other 60x or external L2
controller requires the address tenure to be retried.
BG0
Bus grant 0
1
O
Indicates that the primary 60x may, with the proper qualification, begin
a bus transaction and assume mastership of the address bus.
BR0
Bus request 0
1
I
Indicates that the primary 60x requires the bus for a transaction.
CI
Cache inhibit
1
I/O
Indicates that an access is caching-inhibited.
DBG0
Data bus grant 0
1
O
Indicates that the 60x may, with the proper qualification, assume
mastership of the data bus.
DBGLB
Local bus slave
data bus grant
1O
Indicates that the 60x processor is prepared to accept data and the
local bus slave should drive the data bus.
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