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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 5/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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13
TSPC106A
2102C–HIREL–01/05
External L2 Controller Signals When an external L2 cache controller is used instead of the internal L2 cache controller,
four signals change their functions.
DOE
DBGL2
Data RAM output
enable
1
O
Indicates that the L2 data RAMs should drive the data bus
DWE[0:2]
DBG2
DBG3
Data RAM write
enable
3
O
Indicates that a write to the L2 data RAMs is in progress. Multiple pins
are provided to reduce loading
HIT
Hit
1
I
Indicates that the L2 cache has detected a hit. The polarity of HIT is
programmable
TOE
DBG1
Tag output enable
1
O
Indicates that the tag RAM should drive the L2 tag address onto the
address bus.
TV
BR2
Tag valid
1
I/O
Indicates that the current L2 cache line should be marked valid. The
polarity of TV is programmable
TWE
BG2
Tag write enable
1
O
Indicates that the L2 tag address, valid, and dirty bits should be
updated
Table 3. Internal L2 Controller Signals (Continued)
Signal
Signal Name
Number of
Pins
I/O
Signal Description
Table 4. External L2 Controller Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
BGL2
BA1
BAA
External L2 bus
grant
1
O
Indicates that the external L2 controller has been granted mastership
of the 60x address bus
BRL2
ADS
DALE
External L2 bus
request
1
I
Indicates that the external L2 controller requires mastership of the 60x
bus for a transaction
DBGL2
DOE
External L2 data
bus grant
1
O
Indicates that the external L2 controller has been granted mastership
of the 60x data bus
HIT
External L2 hit
1
I
Indicates that the current transaction is claimed by the external L2
controller. The external L2 controller will assert AACK and TA for the
transaction
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