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参数资料
| 型号： | TSPC106AVGS66CG |
| 厂商： | E2V TECHNOLOGIES PLC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, CBGA303 |
| 封装： | 21 X 25 MM, 3.84 MM HEIGHT, 1.27 MM PITCH, CICGA-303 |
| 文件页数： | 7/41页 |
| 文件大小： | 581K |
| 代理商： | TSPC106AVGS66CG |
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15
TSPC106A
2102C–HIREL–01/05
Memory Interface
Signals
Table 6 lists the memory interface signals and provides a brief description of their func-
tions. The memory interface supports either standard DRAMs or EDO DRAMs, and
either standard ROMs or Flash ROMs. Some of the memory interface signals perform
different functions depending on the RAM and ROM configurations.
Table 6. Memory Interface Signals
Signal
Signal Name
Number of
Pins
I/O
Signal Description
AR0
MA0
ROM address 0
8
O
Represents address bit 0 of the 8-bit ROM/Flash. Note that AR0 is only
supported for ROM bank 0 when configured for an 8-bit ROM/Flash data
bus width. The extra address bit allows for up to 2 Mbytes of ROM when
using the 8-bit wide data path. Bits 1 - 8 of the ROM address are provided
by AR[1:8] and bits 9 - 20 of the ROM address are provided by AR[9:20].
AR[1:8]
PAR[0:7]
ROM address 1 - 8
8
O
Represents bits 1 - 8 of the ROM/Flash address. The other ROM address
bits are provided by AR0 and AR[9:20].
AR[9:20]
MA[1:12]
ROM address
9 - 20
12
O
Represents bits 9 - 20 of the ROM/Flash address (the 12 lowest order bits,
with AR20 as the least significant bit (lsb)). Bits 0 - 8 of the ROM address
are provided by AR0 and AR[1:8].
BCTL[0:1]
Buffer control 0 - 1
2
O
Used to control external data bus buffers (directional control and high-
impedance state) between the 60x bus and memory. Note that external
data buffers may be optional for lightly loaded data buses, but buffers are
required whenever an L2 cache and ROM/Flash (on the 60x/memory bus)
are both in the system or when ECC is used.
CAS[0:7]
Column address
strobe 0 - 7
8
O
Indicates a memory column address is valid and selects one of the
columns in the row. CAS0 connects to the most significant byte select.
CAS7 connects to the least significant byte select.
FOE
Flash output
enable
1
O
Enables Flash output for the current read access.
MA0
MA[1:12]
AR0
AR[9:20]
Memory address
0 - 12
13
O
Represents the row/column multiplexed physical address for DRAMs or
EDOs (MA0 is the most significant address bit; MA12 is the least significant
address bit). Note that MA0 also functions as the ROM address signal AR0
and MA[1:12] function as the ROM address signals AR[9:20].
MDLE
Memory data latch
enable
1
O
Enables the external, latched data buffer for read operations, if such a
buffer is used in the system.
PAR[0:7]
AR[1:8]
Data parity/ECC
8
O
Represents the byte parity or ECC being written to memory (PAR0 is the
most significant bit).
I
Represents the byte parity or ECC being read from memory (PAR0 is the
most significant bit).
PPEN
Parity path read
enable
1
O
Enables external parity/ECC bus buffer or latch for memory read
operations.
RAS[0:7]
Row address
strobe 0 - 7
8
O
Indicates a memory row address is valid and selects one of the rows in the
bank.
RCS0
ROM/Flash bank 0
select
1
O
Selects ROM/Flash bank 0 for a read access or Flash bank 0 for a read or
write access.
RCS1
ROM/Flash bank 1
select
1
O
Selects ROM/Flash bank 1 for a read access or Flash bank 1 for a read or
write access.
RTC
Real-time clock
1
I
External clock source for the memory refresh logic when the TSPC106 is in
the suspend power-saving mode.
WE
Write enable
1
O
Enables writing to DRAM, EDO or Flash.
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